Andreas Merentitis

Dr. Andreas Merentitis received the B.Sc., M.Sc., and Ph.D. degrees from the Department of Informatics and Telecommunications, National Kapodistrian University of Athens (NKUA) in 2003, 2005, and 2010 respectively. He holds an award from the Greek Mathematical Society and received a scholarship as one of the two highest graded graduates of the M.Sc. in Microelectronics. For the past 6 years, he serves as a Research Fellow in the Communication Networks Laboratory at the NKUA and has participated in the European ICT Integrated Projects E2R I, E2R II, E3 and the European STREP Projects PHYDYAS, SACRA (sub-workpackage leader) and CONSERN (sub-workpackage leader). He has more than 20 publications in the thematic areas of reliability and fault tolerance, beyond 3G systems and power/energy optimization, including publications in flagship conferences and journals. He is a member of the IEEE and the IEEE Computer and Communication Societies, as well as the IEEE Standards Association.

Currently at: AGT Germany
More on his dblp page

Journals / Magazines

• “An Input Vector Monitoring Concurrent BIST Architecture Based on a Pre-computed Test Set”, I. Voyiatzis, A. Paschalis, D. Gizopoulos, C. Halatsis, E. Marki, M. Hatzimihail, IEEE Transactions on Computers, vol. 57, no. 8, pp. 1012-1022, Aug. 2008
• “Systematic Software-Based Self-Test for Pipelined Processors”, D.Gizopoulos, M.Psarakis, M.Hatzimihail, M.Maniatakos, A.Paschalis, A.Raghunathan, S.Ravi, IEEE Transactions on Very Large Scale Integration Systems, vol. 16, no. 11, pp. 1441-1453, Nov. 2008
• “Functional Processor-Based Testing of Communication Peripherals in Systems-on-Chip”, A. Apostolakis, M. Psarakis, D. Gizopoulos, A. Paschalis, IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no.8, Aug. 2007
• N. Kranitis, A. Merentitis, G. Theodorou, A. Paschalis, D. Gizopoulos, “Hybrid Software-Based Self-Test (H-SBST): Methodology and Application on a Modern Processor Core”, IEEE Design & Test of Computers, vol.25, no.1, pp.64-75, Jan-Feb 2008
• “Testability Analysis and Scalable Test Generation for High-Speed Floating Point Units”, G.Xenoulis, D.Gizopoulos, M.Psarakis and A.Paschalis, IEEE Transactions on Computers, vol. 55, no. 11, Nov. 2006, pp. 1449-1457.
• “Accumulator-Based Test Generation for Robust Sequential Fault Testing in DSP Cores in Near-Optimal Time”, I. Voyiatzis, D. Gizopoulos, A. Paschalis, IEEE Transactions on VLSI Systems, vol. 13, no.9, pp. 1079-1086, Sept 2005.
• N. Kranitis, A. Paschalis, D. Gizopoulos, G. Xenoulis, “Software-Based Self-Testing of Embedded Processors”, IEEE Transactions on Computers, vol. 54, no. 4, pp. 461-475, April 2005 (pdf)
• I. Voyiatzis, A. Paschalis, D. Gizopoulos, N. Kranitis, C. Halatsis, “A concurrent built-in self-test architecture based on a self-testing RAM”, IEEE Transactions on Reliability, vol. 54, no. 1, pp. 69-78, March 2005 (pdf)
• “Built-In Sequential Fault Self-Testing of Array Multipliers”, M. Psarakis, D. Gizopoulos, A. Paschalis, IEEE Transactions on CAD of Integrated Circuits and Systems, vol. 24, no. 3, pp. 449-460, March 2005.
• “Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors”, A. Paschalis, D. Gizopoulos, IEEE Transactions on CAD of Integrated Circuits and Systems, DATE’04 Special Issue, Invited Paper, vol. 24, no.1, pp. 88-99, Jan. 2005.
• I. Voyiatzis, N. Kranitis, D. Gizopoulos, A. Paschalis, C. Halatsis, “Accumulator-based built-in self-test generator for robustly detectable sequential fault testing”, IEE Proceedings – Computers and Digital Techniques, vol.151, no.6, pp. 466-472, Nov. 2004 (pdf)
• N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Low-cost software-based self-testing of RISC processor cores”, IEE Proceedings – Computers and Digital Techniques, Invited Paper, Special Issue on the ACM/IEEE Design, Automation and Test in Europe Conference (DATE’03), vol. 150 , no. 5 , pp. 355-360, Sept. 2003 (pdf)
• “Easily Testable Cellular Carry Lookahead Adders”, D.Gizopoulos, M.Psarakis, A.Paschalis, Y.Zorian, Journal of Electronic Testing: Theory and Applications, Kluwer Academic Publishers/IEEE Computer Society, vol. 19, no. 3, pp. 285-298, June 2003.
• N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian, “Instruction-Based Self-Testing of Processor Cores”, Springer Journal of Electronic Testing: Theory and Applications (JETTA), Invited Paper, Special Issue on the 20th IEEE VLSI Test Symposium, vol. 19, no. 2, pp. 103-112, April 2003 (pdf)
• N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis and Y. Zorian, “An Effective Deterministic BIST Scheme for Shifter/Accumulator Pairs in Datapaths”, Springer Journal of Electronic Testing, Theory and Applications (JETTA) , vol. 17, pp. 97-107, April 2001 (pdf)
• N. Kranitis, D. Gizopoulos, A. Paschalis, M. Psarakis and Y. Zorian, “Power/Energy Efficient Built-In Self-Test Schemes for Processor Datapaths”, IEEE Design & Test of Computers, Special Issue on Microprocessor Test and Verification, vol. 17, no. 4, pp. 15-28, October-December 2000 (pdf)
• “Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays”, M. Psarakis, D. Gizopoulos, A. Paschalis, and Y. Zorian, IEEE Transactions on Computers, vol. 49, no. 10, Oct. 2000, pp. 1083-1099.
• “Accumulator-Based BIST Approach for Two-Pattern Testing”, I. Voyiatzis, A. Paschalis, D. Nikolos, and C. Halatsis. Journal of Electronic Testing, Theory and Applications, vol. 15, no. 3, Dec. 1999, pp. 267-278.
• “An Effective Built-In Self-Test Scheme for Array Multipliers”, D. Gizopoulos, A. Paschalis and Y. Zorian. IEEE Transactions On Computers, vol. 48, no. 9, Sept. 1999, pp. 936-950.
• “On Robust Two-Pattern Testing of One-Dimensional CMOS Iterative Logic Arrays”, D. Gizopoulos, A. Paschalis, D. Nikolos and C. Halatsis. International Journal of Electronics, vol. 86, no. 8, Aug. 1999, pp. 967-978.

Refereed Conferences and Workshops

• A. Merentitis, N. Kranitis, A. Paschalis, D. Gizopoulos, “Low Energy On-Line SBST of Embedded Processors”, in proceedings of the International Test Conference (ITC 2008), paper 12.1, 2008.
• A. Merentitis, N. Kranitis, A. Paschalis, D. Gizopoulos, “Selecting Power-Optimal SBST Routines for On-Line Processor Testing”, in Proceedings of the 12th IEEE European Test Symposium (ETS’07), May 2007, pp.111-116 (pdf)
• P. Kenterlis, N. Kranitis, A. Paschalis, D. Gizopoulos, M. Psarakis, “A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs”, in Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS’06), July 2006, pp. 235-241 (pdf)
• N. Kranitis, A. Merentitis, N. Laoutaris, G. Theodorou, A. Paschalis, D. Gizopoulos, C. Halatsis, “Optimal Periodic Testing of Intermittent Faults In Embedded Pipelined Processor Applications”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2006 (DATE’06), March 2006, pp. 65-70 (pdf)
• N. Kranitis, G. Xenoulis, A. Paschalis, D. Gizopoulos, Y. Zorian, “Application and Analysis of RT-Level Software-Based Self-Testing for Embedded Processor Cores”, in Proceedings of the IEEE International Test Conference 2003 (ITC’03), October 2003, pp. 431-440 (pdf)
• G. Xenoulis, D. Gizopoulos, N. Kranitis, A. Paschalis, “Low-Cost On-Line Software-Based Self-Testing of Embedded Processor Cores”, in Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS’03), July 2003, pp.149-154 (pdf)
• N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Low-Cost Software-Based Self-Testing of RISC Processor Cores”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2003 (DATE’03), March 2003, pp. 714-719 (Best Paper Award Nomination)(pdf)
• N. Kranitis, G. Xenoulis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Software-Based Self-Testing of Large Register Banks in RISC Processor Cores”, in Proceedings of the 4th IEEE Latin-American Test Workshop (LATW’03), January 2003
• G. Xenoulis, N. Kranitis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Embedded Software-Based Self-Testing of Processor Cores: Application to a RISC Architecture”, in Proceedings of the 3rd IEEE International Workshop on Test Resource Partitioning (TRP02), October 2002
• Y. Voyiatzis, N. Kranitis, A. Paschalis, D. Gizopoulos, C. Halatsis, “ALU-based Built-In Self Test Generator for Transition Fault Testing”, in Proceedings of the 7th IEEE European Test Workshop (ETW’02), May 2002
• N. Kranitis, D. Gizopoulos, A. Paschalis, Y. Zorian, “Instruction-Based Self-Testing of Processor Cores”, in Proceedings of the 20th IEEE VLSI Test Symposium (VTS’02), April 2002, pp.223-228(pdf)
• N. Kranitis, A. Paschalis, D. Gizopoulos, Y. Zorian, “Effective Software Self-Test Methodology for Processor Cores”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2002 (DATE’02), March 2002, pp. 592-597 (pdf)
• M. Psarakis, D. Gizopoulos, A. Paschalis, N. Kranitis and Y. Zorian, “Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers”, in Proceedings of the 19th IEEE VLSI Test Symposium (VTS’01), April 2001, pp. 15-20 (pdf)
• N. Kranitis, M. Psarakis, D. Gizopoulos, A. Paschalis, Y. Zorian, “An effective deterministic BIST scheme for Shifter/Accumulator pairs in datapaths”, in Proceedings of the 2nd IEEE International Symposium on Quality Electronic Design (ISQED’01), March 2001, pp. 343-349 (pdf)
• A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, Y. Zorian, “Deterministic Software-Based Self-Testing of Embedded Processor Cores”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2001 (DATE’01), Munich, March 2001, pp. 92-96 (pdf)
• A. Paschalis, N. Kranitis, D. Gizopoulos, M. Psarakis, Y. Zorian, “Effective Deterministic Arithmetic BIST Architecture for Embedded Processor Cores”, in Proceedings of the 4th IEEE International Workshop on Testing Embedded Core-based System-Chips (TECS’00), May 2000
• D. Gizopoulos, N. Kranitis, A. Paschalis, M. Psarakis, and Y. Zorian. “Low Power/Energy BIST Scheme for Datapaths”, in Proceedings of the 18th IEEE VLSI Test Symposium (VTS’00), April 2000, pp. 23-28 (pdf)
• D. Gizopoulos, N. Kranitis, A. Paschalis, M. Psarakis, and Y. Zorian, “Effective Low Power BIST for Datapaths”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 2000 (DATE’00), March 2000, p.757 (poster) (pdf)
• M. Psarakis, N. Kranitis, D. Gizopoulos, A. Paschalis, and Y. Zorian “Deterministic Built-In Self-Test for Shifters, Adders and ALUs in Datapaths”, in Proceedings of the 1st IEEE Latin-American Test Workshop (LATW’00), March 2000
• D. Gizopoulos, M. Psarakis, A. Paschalis, N. Kranitis and Y. Zorian, “Low Power Built-In Self-Test for Datapath Architectures”, in Proceedings of the 2nd IEEE International Workshop on Microprocessor Test and Verification (MTV’99), Oct. 1999
• N. Kranitis, M. Psarakis, A. Paschalis, D. Gizopoulos, and Y. Zorian, “Built-In-Self-Test for Shifter – ALU pairs in Datapaths”, in Proceedings of the 5th IEEE On-Line Testing Workshop (IOLTW’99), July 1999, pp. 92-96
• A. Paschalis, D. Gizopoulos, N. Kranitis, M. Psarakis, and Y. Zorian. “An Effective BIST Architecture for Fast Multiplier Cores”, in Proceedings of the ACM/IEEE Design, Automation and Test in Europe Conference 1999 (DATE’99), March 1999, pp.117-121 (pdf)